This invention relates to the implementation of a digital speech synthesis system which utilizes a miniature electronic semiconductor device or chip comprising an integrated circuit speech synthesizer for digitally synthesizing human speech.
Several techniques are known in the prior art for digitizing human speech. For example, pulse code modulation, differential pulse code modulation, adaptive predictive coding, delta modulation, channel vocoders, cepstrum vocoders, format vocoders, voice excited vocoders and linear predictive coding techniques of speech digitalization are known. The techniques are briefly explained in "Voice Signals: Bit by Bit" on pages 28-34 of the October 1973 issue of IEEE Spectrum.
In certain applications and particularly those in which the digitized speech is to be stored in a memory, most researchers tend to use the linear predictive coding technique because it produces very high quality speech using rather low data rates. Linear predictive coding systems usually make use of a multi-stage digital filter. In the past, the digital filter has typically been implemented by appropriately programming a large scale digital computer. However, there has been a proposal for implementing a speech synthesis chip which is discussed in "Progress in the Development of Digital Vocoder Employing an Itakura Adaptive Predictor" published in "Telecommunications Conference Records", IEEE publication no. 73 (1973). In U.S. Pat. No. 4,209,844 there is taught a particularly useful digital filter for a speech synthesis circuit, which digital filter may be implemented on an integrated circuit using standard MOS or equivalent technology. A theoretical discussion of linear predictive coding can be found in "Speech Analysis and Synthesis by Linear Prediction of the Speech Wave" at Volume 50, number 2 (part 2) of The Journal of the Acoustical Society of America.
Disclosed herein is a talking learning aid which utilizes speech synthesis technology for producing human speech. A complete talking learning aid is disclosed, so, in addition to describing the speech synthesis circuits in detail, the details of the controller for the learning aid and the Read-Only-Memory devices used to store the digitized speech are also disclosed. Of course, those practicing the present invention may wish to practice the invention in conjunction with a talking learning aid, such as that described herein, other learning aids or in any other application wherein the generation of human speech from digital data is desirable. Using the techniques described in the aforementioned U.S. Pat. No. 4,209,844 and the teachings disclosed herein will permit those desiring to make use of digital speech technology to do so with one, or a small number, of relatively inexpensive integrated circuit devices.
This invention relates to a speech synthesis system which includes a small size integrated circuit or chip for digitally synthesizing human speech, as previously mentioned. An object of this invention was to improve speech synthesis technology. Another object was to implement a digital speech synthesis system by employing as a component thereof a speech synthesizer chip on a small size integrated circuit which chip can be produced using conventional fabrication techniques. It was yet another object of this invention to bring digital speech synthesis technology into a price range where the ordinary consumer may take advantage of it.
The foregoing objects are achieved as is now described. The system includes a speech synthesis chip which includes a linear predictive filter, excitation generators, circuits for receiving and analyzing inputted digital data and appropriate timing circuitry, all of which are integrated on a single semiconductor chip. The linear predictive filter comprises only a single filter stage containing a single multiplier for selectively multiplying a plurality of coefficients, initiating the multiplication of one coefficient at a time, by using a feedback loop with multiplexing techniques so as to input multiplexed signals to the multiplier. Thus, the single multiplier of the linear predictive filter is utilized repetitively to provide the calculations required.